Development of VLSI Technology

Development of VLSI Technology CHAPTER 1 1. INTRODUCTION The VLSI was an important pioneer in the electronic design automation industry. The â€Å"lambda-based† design style which was advocated by carver mead and Lynn Conway offered a refined packages of tools.. VLSI became the early hawker of standard cell (cell-based technology). Rapid advancement in VLSI technology has lead to a new paradigm in designing integrated circuits where a system-on-a-chip (SOC) is constructed based on predesigned and pre-verified cores such as CPUs, digital signals processors, and RAMs. Testing these cores requires a large amount of test data which is continuously increasing with the rapid increase in the complexity of SOC. Test compression and compaction techniques are widely used to reduce the storage data and test time by reducing the size of the test data. The Very large scale integration design or manufacturing of extremely small uses complex circuitry of modified semiconductor material. In 1959- jack St. Claire Kilby (Texas instruments) they developed the first integrated circuit of 10 components on 9 mm2. In 1959, Robert Norton Noyce (founder, Fairchild semiconductor) has improved this integrated circuit which has been developed by Jack St Claire Kilby, in 1968- Noyce, Gordon E. Moore found Intel, in 1971- Ted Hoff (Intel) has developed the first microprocessor (4004) consists of 2300 transistors on 9 mm2, since then the continuous improvement in technology has allowed for increased performance as predicted by Moores law. The rate of development of VLSI technology has historically progressed hand-in-hand with technology innovations. Many conventional VLSI systems as a result have engendered highly specialized technologies for their support. Most of the achievements in dense systems integration have derived from scaling in silicon VLSI process. As manufacturing has improved, it has become more cost-effective in many applications to replace a chip set with a monolithic IC: package costs are decreased, interconnect path shrink, and power loss in I/O drivers is reduced. As an example consider integrated circuit technology: the semi conductor industry Association predicts that, over the next 15 years, circuit technology will advance from the current four metallization layers up to seven layers. As a result, the phase of circuit testing in the design process is moving to the head as a major problem in VLSI design. In fact, Kenneth M, Thompson, vice president and general manager of the Technology, Manufactur ing, and Engineering Group for Intel Corporation, states that a major falsehood of testing is that â€Å"we have made a lot progress in testing† in reality it is very difficult for testing to keep speed with semi conductor manufacturing technology. Todays circuits are expected to perform a very broad range of functions as it also meets very high standards of performance, quality, and reliability. At the same time practical in terms of time and cost. 1.1 Analog Digital Electronics In science, technology, business, and, in fact, most other fields of endeavor, we are constantly dealing with quantities. In the most physical systems, quantities are measured, monitored, recorded, manipulated, arithmetically, observed. We should be able to represent the values efficiently and accurately when we deal with various quantities. There are basically two ways of representing the numerical value of quantities: analog and digital 1.2 Analog Electronics Analogue/Analog electronics are those electronic systems with a continuously variable signal. In contrast, two different levels are usually taken in digital electronics signals. In analog representation a quantity is represented by a voltage, current, or meter movement that is comparative to the value of that quantity. Analog quantities such as those cited above have n important characteristic: they can vary over a continuous range of values. 1.3 Digital Electronics In digital representation the quantities are represented not by proportional quantities but by symbols called digits. As an example, consider the digital watch, which provides the time of day in the form of decimal digits which represent hours and minutes (and sometimes seconds). As we know, the time of day changes continuously, but the digital watch reading does not change continuously; rather, it changes in steps of one per minute (or per second). In other words, this digital representation of the time of day changes in discrete steps, as compared with the representation of time provided by an analog watch, where the dial reading changes continuously. Digital electronics that deals with â€Å"1s and 0s†, but thats a vast oversimplification of the in and outs of going digital. Digital electronics operates on the premise that all signals have two distinct levels. Certain voltages might be the levels near the power supply level and ground depending on the type of devices used. The logical meaning should not be mixed with the physical signal because the meaning of this signal level depends on the design of the circuit. Here are some common terms used in digital electronics: Logical-refers to a signal or device in terms of its meaning, such as â€Å"TRUE† or â€Å"FALSE† Physical-refers to a signal in terms of voltage or current or a devices physical characteristics HIGH-the signal level with the greater voltage LOW-the signal level with the lower voltage TRUE or 1-the signal level that results from logic conditions being met FALSE or 0-the signal level that results from logic conditions not being met Active High-a HIGH signal indicates that a logical condition is occurring Active Low-a LOW signal indicates that a logical condition is occurring Truth Table-a table showing the logical operation of a devices outputs based on the devices inputs, such as the following table for an OR gate described as below 1.4 Number Systems Digital logic may work with â€Å"1s and 0s†, but it combines them into several different groupings that form different number systems. Most of are familiar with the decimal system, of course. Thats a base-10 system in which each digit represents a power of ten. There are some other number system representations, Binary-base two (each bit represents a power of two), digits are 0 and 1, numbers are denoted with a ‘B or ‘b at the end, such as 01001101B (77 in the decimal system) Hexadecimal or ‘Hex-base 16 (each digit represents a power of 16), digits are 0 through 9 plus A-B-C-D-E-F representing 10-15, numbers are denoted with ‘0x at the beginning or ‘h at the end, such as 0x5A or 5Ah (90 in the decimal system) and require four binary bits each. A dollar sign preceding the number ($01BE) is sometimes used, as well. Binary-coded decimal or BCD-a four-bit number similar to hexadecimal, except that the decimal value of the number is limited to 0-9. Decimal-the usual number system. Decimal numbers are usually denoted by‘d at the end, like 24d especially when they are combined with other numbering systems. Octal-base eight (each digit represents a power of 8), digits are 0-7, and each requires three bits. It is rarely used in modern designs. 1.5 Digital Construction Techniques Building digital circuits is somewhat easier than for analog circuits-there is fewer components and the devices tend to be in similarly sized packages. Connections are less susceptible to noise. The trade-off is that there can be many connections, so it is easy to make a mistake and harder to find them. There are a few visual clues as result of uniform packages. 1.5.1 Prototyping Boards Prototypes is nothing but putting together some temporary circuits, or, as part of the exercises using a common workbench accessory known as a prototyping board. A typical board is shown in Figure 1 with a DIP packaged IC plugged into the board across the centre gap. This board contains sets of sockets in rows which are connected mutually for the component leads to be connected and plugged in without soldering. Apart from these outer edges of the board which contains long rows of sockets are also connected together so that they can be used for ground connections and power supply which are common to most components. Assembling wiring layout on the prototype board should be carried out systematically, similar to the schematic diagram shown. 1.5.2 Reading Pin Connections IC pins are almost always arranged so that pin 1 is in a corner or by an identifying mark on the IC body and the sequence increases in a counter-clockwise sequence looking down on the IC or â€Å"chip† as shown in Figure 1. In almost all DIP packages, the identifying mark is a dot in the corner marking pin 1. Both can be seen in the diagram, but on any given IC only one is expected to be utilised. 1.5.3 Powering Digital Logic Where analog electronics is usually somewhat flexible in its power requirements and tolerant of variations in power supply voltage, digital logic is not nearly so carefree. Whatever logic family you choose, you will need to regulate the power supply voltages to at least  ±5 percent, with adequate filter capacitors to filter out sharp sags or spikes. To provide references to the internal electronics that sense the low or high voltages and also act on them as logic signals, the logic devices rely on stable power supply voltages. The device could be confused and also misinterpret the inputs if the devices ground voltage is kept away from 0 volts, which in turn causes temporary changes in the signals, popularly known as glitches. It is better to ensure that the power supply is very clean as the corresponding outcome can be very difficult to troubleshoot. A good technique is to connect a 10 ~ 100  µF electrolytic or tantalum capacitor and a 0.1  µF ceramic capacitor in parallel across the power supply connections on your prototyping board. CHAPTER 2 2. REVIEW AND HISTORICAL ANALYSIS OF ITERATIVE CIRCUITS As a background research, recent work on iterative circuits was investigated. In this section, seven main proposals from the literature will be reviewed. The first paper by Douglas Lewin published in (1974, pg.76,277), titled Logic Design of Switching Circuits, in this book he states that quite often in combinational logic design, the technique of expressing oral statements for a logic circuit in the form of a truth table is inadequate. He stated that for a simple network, a terminal description will often suffice, but for more complex circuits, and in particular when relay logic is to be employed, the truth table method can lead to a laborious and inelegant solution. 2.1 Example: A logic system could be decomposed into a number identical sub-systems, then if we could produce a design for the sub-system, or cell, the complete system could be synthesized by cascading these cells in series. The outputs of one cell form the inputs to the next one in the chain and so on, each cell is identical except for the first one (and frequently he last one) whose cell inputs must be deduced from the initial conditions. Each cell has external inputs as well as inputs from the preceding cell, which are distinguished by defining the outputs of a cell as its state. Figure 2.1 Iterative Switching Systems The second proposal which will b reviewed was presented by Fredrick J. Hil and Gerald R. Peterson published in (1981, pg. 570), titled Introduction to Switching Theory and Logic Design, in this book, they discussed that iterative network is highly repetitive form of a combinational logic network. The repetitive structure make possible to describe the iterative networks utilizing techniques that already developed for sequential circuits, the author in this books he has limited his discussion to one dimensional iterative networks represented by the cascade or identical cells given in below figure. A typical cell with appropriate input and output notation is given in one more figure below (b). Now note the two distinct types of inputs, i.e., primary inputs from the outside world and secondary inputs from the previous cell in the cascade. And similarly and there are two types of outputs, i.e., primary to the outside world and secondary to the next cell in the cascade. The boundary input s which are at the left of the cascade denoted by us in the same manner as secondary inputs. At some cases the inputs will be constant values. A set of boundary inputs emerges from the right most cell in the cascade. although these outputs are to the outside world, they will be labelled in the same manners secondary outputs. The boundary outputs will be the only outputs of the iterative networks. The third proposal by Barri Wilkinson with Raffic Makki, published in (1992, pg. 72-4) titled -digital design principles, in this book, they discussed about the design and problems of iterative circuits and stated that, there are some design problems which would require a large number of gates if designed as two level circuits. On approach i.e., is to divide each function into a number of identical sub functions which need be performed in sequence and the result of one sub function is used in the next sub function. A design based around the iterative approach is shown in below figure. There are seven logic circuit cells each cell accepts one code word digit and the output from the preceding cell. The cell produces one output, Z, which is a 1 whenever the number of 1s on the two inputs is odd. Hence successive outputs are a 1 when the number of 1s on inputs to that point is odd and the final output is a 1 only when the number of 1s in the whole code word is odd as required. To create an iterative design, the number of cells and the number of data inputs to each cell need to be determined and also the number of different states that must be recognized by the cell. The number of different states will define the number of lines to the next cell (usually carrying binary encoded information). The fourth proposal was reviewed by Douglas Lewin and David Protheroe published in (1992, pg. 369),titled Design of Logic systems, in this book, according to them, iterative networks were widely used in the early days of switching systems when relays were the major means of realizing logic circuits. these technique fell into disuse when electronic logic gates widely available. It is possible to implement an arbitrary logic function in the form of an iterative array, the technique is most often applied to functions which are in the sense ‘regular in that the overall function may be achieved by performing the same operation up to a sequence of a data bits. Iterative cell techniques are particularly well suited to pattern recognition and encoding and decoding circuits with large numbers of parallel inputs. The method is also directly applicable to the design of VLSI circuits and has the advantage of producing a modular structure based on a standard cell which may be optimized independently in terms of layout etc. Circuits containing any number of input variables can easily be constructed by simply extending the network with more cells. they examine the iterative circuits with some examples, although it is possible to implement an arbitrary logic function in the form of an iterative array, the technique is most often applied to functions which are in this sense ‘regular in that the overall function may be achieved by performing the same operation upon a sequence of data bits. Suppose a logic system could be decomposed into a number of identical subsystems; then if we could produce a design for the subsystem, or cell, the complete system could be synthesized by cascading these cells in series. Problem Reduced: this problem now has been reduced to that of specifying and designing the cell, rather than the complete system. The fifth proposal presented by Brians Holdsworth published in (1993, pg. 165-166) titled Digital Logic Design, stated that iterative networks widely used before the introduction of electronic gates are again of some interest to the logic designers as a result of developments in semiconductor technology. Moss pass transistors which are easily fabricated are used in LSI circuits where these LSI circuits require less space and allow higher packing densities. One of the major disadvantages of hard-wired iterative networks was the long propagation delays because of the time taken for signals to ripple through a chain of iterated cells. This is no longer such a significant disadvantage since of the length of the signal paths on an LSI chip are much reduced in comparison with the hard-wired connections between SSI and MSI circuits. However, the number of pass transistors that can be connected in series is limited because of signal degradation and it is necessary to provide intercell buffe rs to restore the original signal levels. One additional advantage is the structural simplicity and the identical nature of the cells which allows a more economical circuit layout. A book proposed by Brians Holdsworth and R.C. Woods published in (2002, pg.135), titled Digital Logic Design, in this book, the discussion on the structure has made and stated that iterative network consists of number of identical cells interconnected in a regular manners as shown in figure with the variables X1.Xn are termed as primary input signals while the output signals termed as Z1Zn and another variable is also taken a1an+1 are termed as secondary inputs or outputs depending on whether these signals are entering or leaving a cell. The structure of an iterative circuit may be defined as one which receives the incoming primary data in parallel form where each cell process the incoming primary and secondary data and generates a secondary output signal which is transmitted to the next cell. Secondary data is transmitted along the chain of cells and the time taken to reach steady state is determined by the delay times of the individual cells and their interconnections. According to Larry L. Kinney, Charles .H and Roth. JR, published in (2004, pg.519) titled Fundamentals of Logic design, in this book they discussed that many design procedures used for sequential circuits can be applied to the design of the iterative circuits, they consists of number of identical cells interconnected in a regular manner. Some operations such as binary addition, naturally lend themselves to realization with an iterative circuit because of the same operation is performed on each pair input bits. The regular structure of an iterative circuit makes it easier to fabricate in integrated circuit from than circuits with less regular structures, the simplest form of a iterative circuit consists of a linear array of combinational cells with signals between cells travelling in only one direction, each cell is a combinational circuit with one or more primary inputs and possibly one or more primary outputs. In addition, each cell has one or more secondary inputs and one or more secondary outputs. Then the produced signals carry information about the â€Å"state† of one cell to the next cell. The primary inputs to the cells are applied in parallel; that is, they are applied at the same time, the signals then propagate down the line of cells. Because the circuit is combinational, the time required for the circuit to reach a steady- state condition is determined only by the delay times of the gates in the cell. As soon as steady state is reached, the output may be read. Thus, the iterative circuits can function as a parallel- input, parallel-output device, in contrast with the sequential circuit in which the input and output are serial. One can think of the iterative circuits as receive its inputs as a sequence in time. Example: parallel adder is an example of iterative circuits that has four identical cells. The serial adder uses the same full adder cell as he parallel adder, but it receives its inputs serially and stores the carry in a flip-flop instead of propagating it from cell to cell. The final proposal was authored by JOHN F WAKERLY, published in (2006, pg. 459, 462, 756), titled Digital Design Principles, in this book he quoted that, iterative circuits is a special type of combinational circuits, with the structure shown in below figure. This circuit contains n identical modules, each of which contains both primary inputs and primary outputs and cascading inputs and cascading outputs. The left most cascading inputs which is shown in below figure are called boundary inputs and are connected to fixed logic values in most iterative circuits. The right most cascading outputs are called boundary outputs and these cascading output provides important information. Iterative circuits are well suited to problems that can be solved by a simple iterative algorithm: Set C0 to its initial value and set i=0 Use Ci and Pli to determine the values of P0i and Ci+1. Increment i. If i In an iterative circuit, the loop of steps 2-4 is â€Å"unwound† by providing a separate combinational circuit that performs step 2 for each value of i. Each of the works reviewed makes an important contribution to improve the disadvantages and problems by iterative circuits, which is lead to improving the iterative circuits, thus it is appealing me to pursue an investigation on the sequential circuits for better understanding about the iterative circuits CHAPTER 3 3. OVERVIEW OF DESIGN METHODS FOR ITERATIVE CIRCUITS 3.1 Iterative design Iterative design is a design methodology based on a cyclic process of prototyping, testing, analyzing, and refining a product or process. Changes and refinements are made, in the most recent iteration of a design, based on the results of testing. The quality and functionality design can be improved by this process. The interaction with the designed system is used as a research for informing and evolving a project, as successive versions in Iterative design. 3.2 Iterative Design Process The iterative design process may be applied throughout the new product development process. In the early stages of development changes are easy and affordable to implement. In the iterative design process the first is to develop a prototype. In order to deliver non-biased opinions the prototype should be examined by a focus group which is not associated with the product. The Information gained from the focus group should be integrated and synthesized into next stage of iterative design. This particular process must be recurred until an acceptable level is achieved for the user. Figure 3.1 Iterative Design Process 3.3 Iterative Circuits Iterative Circuits may be classified as, Combinational Circuits Sequential Circuits. Combinatorial circuit generalized using gates has m inputs and n outputs. This circuit can be built as n different combinatorial circuits, apiece with exactly one output. If the entire n-output circuit is constructed at once then some important sharing of intermediate signals may take place. This sharing drastically decreases the number of gates needed to construct the circuit. In some cases, we might be interested to minimize the number of transistors. In other, we might want a little delay, or we may need to reduce the power consumption. Normally a mixture of such type must be applied. In combinational logic design, the technique of expressing oral statements for a logic circuit in the form of a truth table is inadequate. For a simple network, a terminal description will often suffice, but for more complex circuits, and in particular when relay logic is to be employed, the truth method can lead to laborious and inelegant solutions. Iterative cell techniques are particularly well suited to pattern recognition and encoding and decoding circuits with a large number of parallel inputs, circuits specification is simplified and large variable problems reduced to a more tractable size, this method is directly applicable to the design of VLSI circuits. It should be pointed out though that the speed of the circuit is reduced because of the time required for the signals to propagate along the network; the number of interconnections is also considerably increased. In general, iterative design does not necessarily result in a more minimal circuit. As the advantage of producing a modular structure, circuits containing any number of input variables can be easily constructed by simple extending the networks with more cells. Suppose for example a logic system could be decomposed into number of identical sub subsystems, then if we would produce a design for the subsystem or a cell the complete system could be synthesized by cascading these cells in series. The problem has now been reduced to that of specifying and designing the cell, rather than the complex systems In general, we define a synchronous sequential circuit, or just sequential circuit as a circuit with m inputs, n outputs, and a distinguished clock input. The description of the circuit is made with the help of a state table with latches and flip-flops are the building blocks of sequential circuits. The definition of a sequential circuit has been simplified as the number of different states of the circuit is completely determined by the number of outputs. Hence, with these combinational circuits we are going to discuss a normal method that in the worst case may waste a large number of transistors For a sequential circuit with m inputs and n outputs, our method uses n D-flip-flops (one for each output), and a combinatorial circuit with m + n inputs and n outputs. 3.4 Iterative Circuits-Example An iterative circuit is a special type of combinational circuit, with the structure shown, The above diagram represents the iterative circuits and this circuit contains ‘n identical modules each of which has both primary inputs and outputs and cascading inputs and outputs. The left most cascading inputs are called boundary inputs and are connected to fixed logic values in most iterative circuits. The right most cascading outputs are called boundary outputs and usually provide important information. Quiet often in combinational logic design, the technique of expressing oral statements for a logic circuit in the form of truth table is inadequate. Iterative circuits are well suited to problems that can be solved by an algorithm i.e iterative algorithm Set C0 to initial value and set i to 0. Use Ci and Pli to determine the values of P0i and Ci+1. Increment i. If i In an iterative circuits, the loop of steps 2-4 is â€Å"unwound† by providing a separate combinational circuit that performs step 2 for each value of i. 3.5 Improving the testability of Iterative Circuits As stated by A.Rubio et al, (1989, pg.240-245), the increase in the complexity of the integrated circuits and the inherent increase in the cost of the test carried out on them are making it necessary to look for ways of improving the testability of iterative circuits.The integrated circuits structured as iteration of identical cells, because their regularity have a set of advantages that make them attractive for many applications. Among these advantages are their simplicity of design, because the structural repetition of the basic cell, manufacturing, test, fault tolerance and their interest for concurrent algorithmic structure implementation. Here in this journal we also study about the testability of iterative circuits the below figure illustrates the typical organization of an N-cells iterative unidimensional circuit (all the signals go from left to right); however the results can be extended to stable class of bilateral circuits. The N cells have identical functionality. Every cell (i) has an external input yi and an internal input xi coming from the previous cell (i-1). Every cell generates a circuit output signal yi and an internal output xi that goes to the following cell (i+1).The following assumptions about these signals are considered below All the yi vectors are independent. Only the x1, y1, y2.yn signals are directly controllable for test procedures. Only the y1, y2 yn signals are directly observable. The xi and ^xi signals are called the states (input and output states respectively) of the ith-cell and are not directly controllable (except xi) neither observable (except xn). Kautz gives the condition of the basic cell functionality that warrants the exhaustive testing of each of the cells of the array. These conditions assure the controllability and observability of the states. In circuits that verify these conditions the length of the test increase linearly with the number of cells of the array with a resulting length that is inferior to the corresponding length for other implementation structures. A fundamental contribution to the easy testability of iterative circuits was made by Freidman. In his work the concept of C-testability is introduced; an iterative circuit is C-testable if a cell-level exhaustive test with a constant length can be generated. This means the length is independent of the number of cells composing the array (N). The results are generalised in several ways. In all these works it is assumed that there is only one faulty cell in the array. Cell level stuck-at (single or multiple) and truth-table fault models are considered. The set T of test vectors of the basic cell is formed by a sequence (what ever the order may be) of input vectors to the cell. Kautz proposed the cell fault model (CFM) which was adopted my most researchers in testing ILAs. As assumed by CFM only one cell can be faulty at a time. As long as the cell remains combinational, the output functions of the faulty cell could be affected by the fault. In order to test ILA under CFM every cell should be supplied with all its input combinations. In Addition to this, the output of the faulty cell should be propagated to some primary output of the ILA. Friedman introduced c-testability. An ILA is C-testable if it can be tested with a number of test vectors which are independent of the size of the ILA. The target of research in ILA testing was the derivation of necessary and sufficient conditions for many types of ILAs (one dimensional with or without vertical outputs, two-dimensional, unilateral, bilateral) to be C-testable. The derivations of these conditions were based on the study of flow table of the basic cells of the array. In the case of an ILA which is not C-testable modifications to its flow table (and therefore as to its internal structure) and/or modifications to the overall structure of the array, were proposed to make it C-testable. Otherwise, a test set with length usually proportional to the ILA size was derived (linear testability). In most cases modifications to the internal structure of the cells and/or the overall structure of the ILA increase the area occupied by the ILA and also affect it performance. ILA testing considering sequential faults has been studied, sequential fault detection in ripple carry adders was considered with the target to construct a shortest length sequence. In sufficient conditions for testing one dimensional ILAs for sequential faults were given. It was not shown that whenever the function of basic cell of an ILA is bijective it can be tested with constant number of tests for sequential faults. To construct such a test set like this a procedure was also introduced. The following considerations from the basis of our work. Many of the computer aided design tools are based on standard cells libraries. While testing an ILA, the best that can be done is to test each of its cells exhaustively with respe